VHDL Syntax â€“ Some General Rules
1- VHDL codes are classified as either:
So designers shall take care on choosing codes either for implementation or simulation.
2- VHDL has its own reserved words such as â€ś if, while, and, when, process, with,â€ť etc.
3- VHDL statements can be either:
4- VHDL codes are finalized with (;), e.g.Â Â A<=3;
Note: Symbol â€ś<=â€ť indicates assignments in VHDL. It shall not be confused with greater than or equal to sign of regular software languages.
5- VHDL is not case-sensitive. E.g. â€śtempâ€ť and â€śTEMPâ€ť are the same in synthesizer perspective.
6- Spaces and empty lines are ignored in VHDL. So you can use those to make your code look neater.
A<=Â Â Â Â Â Â Â Â CÂ Â Â and
DÂ Â Â Â ;
A <= C and D;
7- Anything after â€ś--â€ť sign in a line is assumed as comments and ignored by the synthesizer. Comments are short explanations that are used to make the code clear for others and for future use also.
A <= C + D; -- Assign A, the addition of C and DÂ <- So this green part is commented out.