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VHDL Syntax – Some General Rules

 1- VHDL codes are classified as either:

          So designers shall take care on choosing codes either for implementation or simulation.

2- VHDL has its own reserved words such as “ if, while, and, when, process, with,” etc.

3- VHDL statements can be either:

4- VHDL codes are finalized with (;), e.g.   A<=3;

Note: Symbol “<=” indicates assignments in VHDL. It shall not be confused with greater than or equal to sign of regular software languages.

5- VHDL is not case-sensitive. E.g. “temp” and “TEMP” are the same in synthesizer perspective.

6- Spaces and empty lines are ignored in VHDL. So you can use those to make your code look neater.

        A<=            C    and
                         D     ;
        A <= C and D;

7- Anything after “--” sign in a line is assumed as comments and ignored by the synthesizer. Comments are short explanations that are used to make the code clear for others and for future use also.

  A <= C + D;     --  Assign A, the addition of C and D  <- So this green part is commented out.

 

 

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