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Entity defines the interface of a design with its outer environment. It is used to determine the relationship of a model with its interface. This section shows the model's outer border, inputs and outputs. Ports are defined in this construct.

Entity Declaration

entity entity_name is
        Generic declaration;
         Port declaration;
end entity_name;


entity CLOCK is
      generic (Upper_level : integer := 3 ;
                       time_bit: time :=2 ns );
      Port ( CLK : in STD_LOGIC;
                 OUT : out STD_LOGIC);
end CLOCK;

Port Declaration: Input and outputs of the model is declared in this section.

entity entity_name is
    Generic declaration;
      Port ( port_name: port_signal_type value;
                 port _name:port_signal_typevalue);
end entity_name;

Three types of ports can be defined with VHDL.

Generic Declaration:
In this section, some parameters of entity transferred to components. Required information can be entered to the design mode in this way.

You can see more information about generic from here.


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