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 * Entity

 * Architecture

 * Configuration

 * Package

 * Library

  * STD Library

VHDL Design Units

A typical VHDL design consists of 4 sections.

1. Entity

Entity defines the interface of a design with its outer environment. In this section input/output ports are defined.

2. Architecture

This construct is used to define the functionality of the model.

3. Configuration

Configuration determines how all sub-components are combined to become a design and how blocks are connected together.

4. Package

Package is a construction which groups the declarations in order to use them in different designs.






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