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Package

It is a collection of declarations that can be used more than one design. constants, data types, components, functions and subroutines can be defined in package, and thus this can be used in more than one design.

The designer defines shared declarations in the package. Thus the designer can use these declarations in all the modules and sub-designs. So the designer is freed from the trouble of writing the same phrases over and over again.

PackageConstruction

1. Package Declaration: This section is mandatory. declarations of types and sub-programs are located in this mandatory section.

package package_name is
     package_declaration
end package package_name;

2. Package G繹vdesi (Body): This section is optional. It contains definitions of sub-programs.

package body package_name is
     package_body declaration
     sub-programs
     deferred constant declaration
end package body package_name;

Example:

1

Defining a package in the VHDL code is contrary to the intended use of pakage. So it would be more appropriate to define the package in work library or in a created special library.

Xilinx ISE and Quartus II Compiler Package libraries, how to create and work with programs, with the Quartus'da Package Description Package Description of how to use the samples, you can find ISEs, respectively. You can see how a package can be created with Xilinx ISE and Quartus II compiler programs and how you can use it in Pakage Definition with ISE and Package Definition with Quartus examples.

Package Usage

"Use" expression provides to use of declarations (which are defined in packages) in entities.

Use library_name.package_name. All

Example:

library My_library;
use My_library.OR_XOR_AND.all;

 

 

2                                                                                                                                     Vhdl_Code                                                                                                                                    

 

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