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VHDL Terminology

HDL (Hardware Description Language)

HDL is a kind of programming language that is used to model hardware. HDL provides us the capability to configure and define the behavior of the hardware in terms of software. VHDL and Verilog are the most common two HDLs.

Behavioral Modelling

Defines the behavior of the model in terms of input/output relations. The internal structure of the hardware is not specified explicitly but rather left to the synthesizer. The focus is only on the function of the model.


Structural Modelling

Defines the connections between inputs and outputs of the components explicitly. Hence the structure of the model is defined by the designer.
This method allows you to modularize your design, hence it’s extremely useful for large and complex designs.


In VHDL designs, common design method used in practice is to model sub-components as behavioral and then using structural modeling to connect those to each other in upper layer.

Register Transfer Level (RTL) 

RTL is a kind of structural modeling in which the design is defined in terms of Register Transfers. VHDL is converted to RTL by synthesizers and usually you don’t need to go down to RTL level unless you’re doing a very advanced intervention in your design.

Synthesis

Conversion of HDL code to hardware implementation.


Process

Basic processing unit in VHDL code. 

A Simple Example to understand basic design method in VHDL – Behavioral vs. Structural Modeling

 

 

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