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 * Constant

 * Signal

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 * Component

 * Concurrent Assignments

 * Process

 * Sequential Statements

 * Variable

  * User Defined Types

 

Component

Component represents entity-architecture pare. It assigns a sub-system which wil be instantiated in another architecture. Simply, a component allows us to include modules created with structurel design, into the main VHDL program.

Instantiating a component is similar to insert an IC to a socket on a board.

Component Declaration

component component_name
generic ( generic_name : type := value;
other genericsr... );
port         ( port_name : mode :=type;
       other ports... );
end component ;


Component Insatantition in Main Program

Label : component name
generic map ( generic_name => value,
dier generic... )
port map ( port_name> => signal_name,
other ports.. );

You can see an example about components from here.

 

 

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