FINITE STATE MACHINE (FSM)
FSM is used to model the communication between the limited number of states. This communication is based on the state at that time and the inputs coming from outside. This is the most common method used in FPGA programming.
Output of the Mealy Machine is a function of output state and the input coming from outside.
Moore machine :
Output of the Moore Machine is only a function of state.
You can understand better the relation between Mealy Machine and Moore Machine in edge_detector-FSM example.
ASM chart consists of state box, desicion box and conditional output boxes.
State Diagram consists of nodes and the links between this nodes (transitional arcs). Nodes are represented by circles and it contains state name and the assignments related to this state.
Links represent the conditions between nodes and the assignments during the changes between nodes.