FPGA Center

  * JK Flip-Flop

   * Example


JK is one of the most used flip-flops in digital design. It has two inputs labeled J and K. If J and K are both “0” then no change occurs. If J and K are both “1” at the clock edge then the output will toggle from one state to the other. It means that the output changes its value when both inputs are high.

Therefore the limitation that is seen when using the latches is get rid off .

JK flip-flop’ta, J ve K girişlerin her ikisi “1” olduğunda çıkış bir önceki değerin tersini alır. Böylelikle Lachler'de bulunan kısıtlama da ortadan kaldırılmış olur. (As you remember, the output is not defined /not used when R and S are both high.)

Truth Table


library IEEE;

entity jk_flip_flop is
    Port ( J         : in  STD_LOGIC;
              K         : in  STD_LOGIC;
              Clk      : in  STD_LOGIC;
              Q_out : out  STD_LOGIC);
   end jk_flip_flop;

architecture Behavioral of jk_flip_flop is
    signal Q:std_logic:=’0’;
             variable JK:std_logic_vector(1 downto 0);
                  wait until (Clk'event and Clk='1');
                     JK:= J&K;
                      case JK is
                          when "01" => Q <= '0';
                          when "10" => Q <= '1';
                          when "11" => Q <= not Q;
                          when others =>  null;
                     end case; 
        end process;
end Behavioral;

After simulating this code with ModelSim, you will get a plot below.





Home | Fpga | VHDL | VHDL Dictionary | Digital Design | Simulation | PCB | Examples | Contact Us
Copyright © 2010 - 2013 FPGAcenter. All Rights Reserved.