JK is one of the most used flip-flops in digital design. It has two inputs labeled J and K. If J and K are both â0â then no change occurs. If J and K are both â1â at the clock edge then the output will toggle from one state to the other. It means that the output changes its value when both inputs are high.
Therefore the limitation that is seen when using the latches is get rid off .
JK flip-flopâta, J ve K giriÅlerin her ikisi â1â olduÄunda Ã§Ä±kÄ±Å bir Ã¶nceki deÄerin tersini alÄ±r. BÃ¶ylelikle Lachler'de bulunan kÄ±sÄ±tlama da ortadan kaldÄ±rÄ±lmÄ±Å olur. (As you remember, the output is not defined /not used when R and S are both high.)
entity jk_flip_flop is
Port ( J : in STD_LOGIC;
K : in STD_LOGIC;
Clk : in STD_LOGIC;
Q_out : out STD_LOGIC);
architecture Behavioral of jk_flip_flop is
variable JK:std_logic_vector(1 downto 0);
wait until (Clk'event and Clk='1');
case JK is
when "01" => Q <= '0';
when "10" => Q <= '1';
when "11" => Q <= not Q;
when others => null;
After simulating this code with ModelSim, you will get a plot below.