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  * Example 1

   * Example 2

LATCHES

Latches are logic gates which hold the value on itself until any external intervention. This feature makes the latches storage elements.

1

Latch (By using NOR gates)

2

Truth Table

3

VHDL Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Latch is
   Port ( Set      : in  STD_LOGIC;
             Reset : in  STD_LOGIC;
             Q         : out  STD_LOGIC;
             Q_n    : out  STD_LOGIC);
end Latch;

architecture Behavioral of Latch is

   begin
      process (Set, Reset)
          begin
             if (Set = '1') then
                   Q <= '1';
                   Q_n<='0';
            elsif (Reset = '1') then
                   Q <= '0';
                   Q_n<='1';
           end if;
      end process;
end Behavioral;

After simulating this code with ModelSim, you will get a plot below.

4

 

 

 

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