FPGA Center



  * Example 1

   * Example 2  

REGISTER TRANSFER

In this example we designed a module that shows how to transfer data between to registers. (Which is the same process that command “MOV A, B” do in assambly.)


VHDL Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity register_transfer is
    Port ( Clk                    : in  STD_LOGIC;
               Move_enable : in  STD_LOGIC;
               Q_in                 : in  STD_LOGIC;
               Q_out               : out  STD_LOGIC;
               Q_n_out          : out  STD_LOGIC);
    end register_transfer;

architecture Behavioral of register_transfer is
    COMPONENT Latch
          PORT( Set      : IN std_logic;
                       Reset : IN std_logic;          
                       Q         : OUT std_logic;
                       Q_n     : OUT std_logic );
    END COMPONENT;

signal Rt, S t:Std_logic;

begin
        Rt<=Move_enable and Clk and Q_in;
        St<=Move_enable and Clk and (not Q_in);
        U1: Latch PORT MAP( Set => St, Reset => Rt, Q => Q_out, Q_n => Q_n_out );
end Behavioral;

 After simulating this code with ModelSim, you will get a plot below.

 

project                                                                                                                                  Test_bench

                                                                                                                                    

 

                                                                                                                                                                                                                                                                   

 

 

Home | Fpga | VHDL | VHDL Dictionary | Digital Design | Simulation | PCB | Examples | Contact Us
Copyright © 2010 - 2013 FPGAcenter. All Rights Reserved.