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  * Example 1  

   * Example 2

12-BIT REGISTER

We designed a 12-bit register that does not have a CLK signal. A dual data bus provides the data connection of this register. This is used for both data receiving and sending.


VHDL Code


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity register_12 is
    Port ( Qin                  : in  STD_LOGIC_VECTOR (11 downto 0);
               Move_bus_a : in  STD_LOGIC;
               Move_a_bus : in  STD_LOGIC;
               Oout                : out  STD_LOGIC_VECTOR (11 downto 0));
    end register_12;

architecture Behavioral of register_12 is

signal Rt, St, q:std_logic_vector(11 downto 0);

COMPONENT Latch
       PORT( Set : IN std_logic;
                     Reset : IN std_logic;         
                     Q : OUT std_logic;
                     Q_n : OUT std_logic );
      END COMPONENT;

begin
    U1:for i in Qin'range  generate
                  St(i)<=Qin(i) and  move_bus_a;
                  Rt(i)<=(not Qin(i)) and  move_bus_a;
          end generate;
   U2:for i in Qin'range   generate
                 U3: Latch PORT MAP( Set =>St(i) , Reset =>Rt(i) , Q => q(i) );
          end generate; 

Out <= q when Move_a_bus='1' else (others=>'Z');
end Behavioral;

After simulating this code with ModelSim, you will get a plot below.

project                                                                                                                                 

                                                                                                                                    

 

                                                                                                                                                                                                                                                                   

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