FPGA Center



 * Inverter

 * AND Gate

 * NAND Gate  

 * OR Gate  

 * NOR Gate  

 * XOR Gate  

 * XNOR Gate  

 * Binary Adder  

 * BCD Adder  

 * Comparator  

  * Priority Encoder

BCD ADDER




We used two modules in the BCD Adder program. First module consists of 4-bit binary adder.  Second module converts the binary sums to BCD. This means that the result is added with 6 (0110) if it is greater than 9.
Yani toplam 9 dan b├╝y├╝k ise, toplam  6 (0110) ile toplanacak.



ADJUST MODUL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.std_logic_unsigned.all;

entity ADJUST is
     Port ( IN1 : in  STD_LOGIC_VECTOR (3 downto 0);
                Cin : in  STD_LOGIC;
                S     : out  STD_LOGIC_VECTOR (3 downto 0);
                Cout : out  STD_LOGIC);
     end ADJUST;

architecture Behavioral of ADJUST is

signal temp:integer range 0 to 15;
    begin
        temp<=conv_integer(IN1);
        S <= IN1 when temp < 9 else IN1 + "0110";
        Cout<=        Cin  when temp<9 else   '1' ;       
   end Behavioral;

BCD MODUL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.std_logic_unsigned.all;

entity BCD_adder is
      Port ( A : in  STD_LOGIC_VECTOR(3 downto 0);
                B : in  STD_LOGIC_VECTOR(3 downto 0);
                S : out  STD_LOGIC_VECTOR(3 downto 0);
                Cin : in  STD_LOGIC;
                Cout : out  STD_LOGIC);
     end BCD_adder;

architecture Behavioral of BCD_adder is

COMPONENT N_BIT_ADDER
      GENERIC(N:INTEGER:=5);
      PORT( Cin : IN std_logic;
                   A : IN std_logic_vector(N-1 downto 0);
                   B : IN std_logic_vector(N-1 downto 0);         
                   S : OUT std_logic_vector(N-1 downto 0);
                   Cout : OUT std_logic );
END COMPONENT;

COMPONENT ADJUST
      PORT( IN1 : IN std_logic_vector(3 downto 0);
                   Cin : IN std_logic;         
                    S : OUT std_logic_vector(3 downto 0);
                    Cout : OUT std_logic );
END COMPONENT;     
 
signal T:std_logic_vector(3 downto 0);
signal C: std_logic;

begin
      BIT_ADDER: N_BIT_ADDER
           GENERIC MAP(N=>4)
           PORT MAP( Cin =>Cin , A => A, B => B, S => T, Cout =>C );
    ADJUST_MODE: ADJUST PORT MAP( IN1 => T, Cin => C, S =>S , Cout => Cout );
end Behavioral;

After simulating this code with ModelSim, you will get a plot below.

project                                                                                                                                  Test_bench

                                                                                                                                    

 

                                                                                                                                                                                                                                                                   

Home | Fpga | VHDL | VHDL Dictionary | Digital Design | Simulation | PCB | Examples | Contact Us
Copyright © 2010 - 2013 FPGAcenter. All Rights Reserved.