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We will add two values. First of all we will design a module that adds two one-bit binary numbers. Then we will see how to add bigger numbers (N bits) by using this module.

1 Bit Adder

Lets draw the truth table first.


We can get the equetion below from the truth table.

Si  = Ai xor Bi xor Ci
Ci+1  = Ai.Bi + Ai.Ci + Bi.Ci = Ai.Bi + (Ai xor Bi).Ci

library IEEE;

entity Bit_Adder is
    Port ( Ci : in  STD_LOGIC;
               Ai : in  STD_LOGIC;
               Bi : in  STD_LOGIC;
               Si : out  STD_LOGIC;
               Cn : out  STD_LOGIC);
   end Bit_Adder;

architecture Behavioral of Bit_Adder is
      Si<=Ai xor Bi xor Ci;
       Cn<=(Ai and Bi) or ((Ai xor Bi) and Ci);
end Behavioral;

After simulating this code with ModelSim, you will get a plot below.

N Bit Adder

In this project, we will use 1-Bit addet modules to form an N-bit adder. Besides we will define the capacity as generic in order to allow user to change the capacity of the adder.

library IEEE;

 entity N_BIT_ADDER is
    generic( N:integer:=5);
    Port ( Cin : in  STD_LOGIC;
               A : in  STD_LOGIC_VECTOR (N-1 downto 0);
               B : in  STD_LOGIC_VECTOR (N-1 downto 0);
               S : out  STD_LOGIC_VECTOR (N-1 downto 0);
               Cout : out  STD_LOGIC);
    end N_BIT_ADDER;

architecture Behavioral of N_BIT_ADDER is
            PORT(Ci : IN std_logic;
                        Ai : IN std_logic;
                        Bi : IN std_logic;         
                        Si : OUT std_logic;
                        Cn : OUT std_logic   );
            END COMPONENT;
signal temp:std_logic_vector(N-2 downto 0);
 U1: for I in A'range generate
                    U2:  if I=A'right generate
                                    U6:Bit_Adder PORT MAP( Ci => Cin ,  Ai => A(I),  Bi => B(I), Si =>S(I) , Cn =>temp(I) );
                                end generate;
                    U3:  if I= A'left generate                                 
                                     U7: Bit_Adder PORT MAP(  Ci => temp(I-1) , Ai => A(I), Bi => B(I), Si =>S(I) , Cn => Cout);
                               end generate;                                  
                    U4: if (I < A'left) and I > A'right generate                             
                                    U8:Bit_Adder PORT MAP( Ci => temp(I-1) , Ai => A(I), Bi => B(I), Si =>S(I) , Cn =>temp(I) );
                                 end generate;
         end generate;
end Behavioral;

After simulating this code with ModelSim, you will get a plot below.

project                                                                                                                                  Test_bench




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