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COMPARATOR

In this section we compared two numbers with respect to their value. First we designed a VHDL module which compares two 1-bit numbers. Then we used this module to compare bigger numbers.

1 Bit Comparator

This module consists of 4 inputs and 2 outputs.

The truth table of the 1-bit comparator is as follows:

 

We get the implication below from the truthtable. (Karnaugh map)

http://www.fpganedir.com/Say%C4%B1sal%20Tasar%C4%B1m/mant%C4%B1k%20kap%C4%B1lar%C4%B1/resim/comparator_clip_image002.jpg
 http://www.fpganedir.com/Say%C4%B1sal%20Tasar%C4%B1m/mant%C4%B1k%20kap%C4%B1lar%C4%B1/resim/comparator_clip_image004.jpg


VHDL Code


library IEEE;
use IEEE.STD_LOGIC_1164.ALL; 

entity comparator_1bit is
    Port ( Ai : in  STD_LOGIC;
               Bi : in  STD_LOGIC;
               Ein : in  STD_LOGIC;
              Gin : in  STD_LOGIC;
              Eout : out  STD_LOGIC;
              Gout : out  STD_LOGIC);
   end comparator_1bit;

architecture Behavioral of comparator_1bit is
    begin
       Eout<= Ein AND (Ai XNOR Bi);
       Gout<= Gin OR (Ein AND Ai AND (NOT Bi));
   end Behavioral;

After simulating this code with ModelSim, you will get a plot below.


N Bit comparator


We used 1-bit comparator modules to form the N-bit comparator. Besides we will define the capacity as generic in order to allow user to change the capacity of the comparator.

VHDL Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; 

 entity comparator_n_bit is
   generic(N:integer:=5);
    Port ( A : in  STD_LOGIC_VECTOR (N-1 downto 0);
              B : in  STD_LOGIC_VECTOR (N-1 downto 0);
              Ei : in  STD_LOGIC;
              Gi : in  STD_LOGIC;
              E : out  STD_LOGIC;
              G : out  STD_LOGIC);
    end comparator_n_bit;

architecture Behavioral of comparator_n_bit is

      COMPONENT comparator_1bit
             PORT(Ai : IN std_logic;
                         Bi : IN std_logic;
                         Ein : IN std_logic;
                         Gin : IN std_logic;         
                         Eout : OUT std_logic;
                         Gout : OUT std_logic  );
            END COMPONENT;
signal T,K:std_logic_vector(N-2 downto 0);
begin
 U1: for I in A'range generate
           begin
                 U2:  if I=A'right generate
                             begin
                              U2: comparator_1bit PORT MAP( Ai => A(I),  Bi => B(I), Ein => T(I),  Gin => K(I),  Eout => E, Gout =>G  );                               end generate;
                 U3:  if I= A'left generate                                 
                            begin
                             U2: comparator_1bit PORT MAP( Ai => A(I), Bi => B(I), Ein => Ei, Gin => Gi, Eout =>T(I-1),  Gout => K(I-1));
                           end generate;                                   
                 U4: if (I < A'left) and I > A'right generate                             
                             begin
                              U2: comparator_1bit PORT MAP( Ai => A(I), Bi => B(I), Ein => T(I),Gin => K(I), Eout =>T(I-1),
                                                                                                                                                                        Gout => K(I-1) );
                            end generate;
       end generate;
end Behavioral;

After simulating this code with ModelSim, you will get a plot below.

project                                                                                                                                  Test_bench

                                                                                                                                    

 

                                                                                                                                                                                                                                                                   

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