FPGA Center

 * Inverter

 * AND Gate

 * NAND Gate  

 * OR Gate  

 * NOR Gate  

 * XOR Gate  

 * XNOR Gate  

 * Binary Adder  

 * BCD Adder  

 * Comparator  

  * Priority Encoder


Priority Encoder, determines the presedence of the defined signals. For example lets think about the CPU of a computer. There are dozens of inputs and outputs providing communication with the CPU.

If all the inputs are active at the same time, processor confused and soes not know which input must be processed first. In order not to allow this kind of chaos, you need to determine the precedence of the inputs to the CPU. A Priority Encoder is used for this kind of tasks.

 The truth table of the 4-input Priority Encoder  is as follows:

Here, Y1 and Yo indicates the status of the inputs and R represents all the inputs are 0.

We get the implication below from the truthtable. (Karnaugh map)



library IEEE;

entity priority_encoder is
    Port ( P3 : in  STD_LOGIC;
               P2 : in  STD_LOGIC;
               P1 : in  STD_LOGIC;
               P0 : in  STD_LOGIC;
               Y1 : out  STD_LOGIC;
               Y0 : out  STD_LOGIC;
                R : out  STD_LOGIC);
end priority_encoder;

architecture Behavioral of priority_encoder is
       Y1<=P3 OR P2;
       Y0<= P3 AND ((NOT P2) AND P1);
       R<=P3 OR P2 OR P1 OR P0;
end Behavioral;

After simulating this code with ModelSim, you will get a plot below.





Home | Fpga | VHDL | VHDL Dictionary | Digital Design | Simulation | PCB | Examples | Contact Us
Copyright © 2010 - 2013 FPGAcenter. All Rights Reserved.