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  * Priority Encoder

XOR GATE



Truth Table

VHDL Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity XOR_GATE is
    Port ( A : in  STD_LOGIC;
               B : in  STD_LOGIC;
               C : out  STD_LOGIC);
    end XOR_GATE;

architecture Behavioral of XOR_GATE is
   begin
        C<=A XOR B;
   end Behavioral;

After simulating this code with ModelSim, you will get a plot below.

project                                                                                                                                  Test_bench

                                                                                                                                    

 

                                                                                                                                                                                                                                                                   

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