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 * Project Definition

 * Create A New Project

 * Create A VHDL Source

 * Simulation

 * Pin Assignment

  * Download To FPGA

Download Design to The FPGA

Compile the project by Double-clicking Generate Programming File in the Process window. During compiler process ,ISE software makes Synthesize-XST, implement Design and Generate Programing File processes respectively and after compilation, ISE creates a .bit extention file which will be downloaded to FPGA.

Double-Click the Manage Configuration Project (IMPACT) under the Configure Target Device in processes window.

 

In IMPACT window change the properties as shown below then click Finish.

Then Assign New Configuration File dialog box appears. To assign a configuration file to your FPGA device in the JTAG chain, select the program file and click Open.

Click Cancel All to skip any remaining devices.

Right-click on the FPGA device image, and select Program and download the program to the FPGA

When programming is complete, the Program Succeeded message is seen.

 

Congratulations... You have finished your first VHDL project.

 

Test Bench                                                                                                                                    

 

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