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Pin Assignment

In this part, each port defined as either input or output in the VHDL Module, is assigned to an FPGA pin. If we don't do this process, compiler makes this assignment randomly.

There are two methods In ISE software for assigning FPGA pins.

1st Method

Select the source file in the sources window by clicking, then In the Processes tab, click the + to expand the User Constraint and double-click the Floorplan -Pre-Synthesis

The Xilinx Pinout and Area Constraints Editor comes. In the Design Object List window, enter a pin location for each pin in the Loc column using the board information. Then save the changes and close the editor.

Not: Assigned pin turns to blue as shown in following shape.

2nd Method

Select Project > New Source. New Source Wizard dialog box appears.
In New Source Wizard dialog box type name of your constraint file in the File name field, Select Implementation Constraints File as the source type and verify that the Add to project checkbox is selected as shown below. Then click Next and Finish.

Click "+" to expand source file and click the constraints file you just created in Sources window then double-click Edit Constraints under the User Constraints in Processes window as shown below.

Enter the ports and pins information as shown below in the constrains file.

Consequently, you have completed FPGA pins assignment. Now you can compile your design and download it to the FPGA.




Test Bench                                                                                                                                     Vhdl_Code


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