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Create A VHDL Source

In this section the Top-Level VHDL file will be created for the design. This VHDL file defines the behavioral description for the comparator module.

Project > New Source... from the menu bar. New Source Wizard window appears.

In New source Wizard dialog box. Type in the File name comparator, Select VHDL Module as the source type and verify that the Add to project checkbox is selected as shown below. Then click Next.

 Fill in the port information as shown below so that you can declare the ports of comparator module.

Click Next, then Finish in the New Source Wizard - Summary dialog box. In this way you have completed the new source file template.

The source file containing the entity/architecture pair displays in the Workspace as shown below:

White the VHDL Code in the workspace.

Note: It is recommended to erase all commands which are written by the program automatically for simplicity.

Check the Syntax of The Comparator Module

After completing the source file you must check it to see any possible errors and typos. If there is any error in source file which shows in the Console tab of the Transcript window, you must correct it. Otherwise you can not simulate or synthesize your design.

To do that, select comparator file in the Sources window, Click the + next to the Synthesize-XST process to expand the process group and Double-click the Check Syntax process.

Now you can simulate your design.

Test Bench                                                                                                                                     Vhdl_Code


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