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Project Definition

In this project, we will design a 1-bit equality comparator.

What will we do in this project?

Introduction

If we write the truth table of the comparator, we will get the table shown below.

By using the truth table, well get the equation as shown below.

Output = In1. In2 +In1'. In2'

The VHDL code of this equation is :


VHDL Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity COMPARATOR is
      Port ( In1      : in STD_LOGIC;
                 In2      : in STD_LOGIC;
                 Output : out STD_LOGIC);
end COMPARATOR;

architecture Behavioral of COMPARATOR is
begin
     Output<=(In1 and In2) or ((not In2) and (not In2));   -- Output=In1.In2 + In1'.In2'
end Behavioral;

This VHDL code determines the behavioral description for the comparator.

 

                                                                                                                                                                             Vhdl_Code

 

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