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 * Simulation

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Simulation

In this section you will create a Test Bench of  VHDL source code for comparator and simulate thisTest Bench with ModelSim software. In this way you will verify the functionality of your comparator module.

Begin the simulation by creating the Test-Bench.

For detailed information about the simulation, see Simulation part.

Select Project > New Source... from menu bar. New Source Wizard dialog box appears.

In New source Wizard dialog box. Type the name of the test bench in the File name, Select VHDL Module as the source type and verify that the Add to project checkbox is selected as shown below. Then click Next.

In Dialog Box select source file which you want to simulate. And click Next and Finish respectively.

ISE software createS a Test Bench template for you.

Correct test bench template as given below.

LIBRARY ieee;
USE
ieee.std_logic_1164.ALL;
USE
ieee.std_logic_unsigned.all;
USE
ieee.numeric_std.ALL;

ENTITY test_bench_my_first IS
END test_bench_my_first;

ARCHITECTURE behavior OF test_bench_my_first IS

    -- Component Declaration for the Unit Under Test (UUT)

  COMPONENT comparator
       PORT( in1 : IN ┬ástd_logic;
               in2 : IN┬á std_logic;
               output : OUT┬á std_logic┬á┬á );
      END COMPONENT;

--Inputs
signal in1 : std_logic := '0';
signal in2 : std_logic := '0';

--Outputs
signal output : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: comparator PORT MAP ( in1 => in1, in2 => in2, output => output );


-- Stimulus process
stim_proc: process
   begin┬á┬á┬á┬á┬á┬á┬á┬á
       wait for 10 ns;┬á┬á┬á┬á┬á
        in1<='1';     
        in2<='0';

       wait for 10 ns;
       in1<='0';
       in2<='1';

      wait for 10 ns;
       in1<='1';
       in2<='1';

     wait for 10 ns;

    --for ending the simulation

      assert false
      report "simulation Overi"
     severity failure;

end process;


Select Behavioral Simulation from the drop-down list in the Sources window. In this way your Test Bench file will be visible in the sources window.

Highlight  the Test Bench file in sources window by right click  then click the ÔÇť+ÔÇŁ next to the Modelsim Simulator expand and Double-click the Simulate Behavioral Model. This process will open the ModelSim software.

Click the Undock icon.

If you don't see the plots below, there is a syntax error in your Test bench program. Check test bench program again and apply steps as related above.

Then click Run All button and begin the simulation.

Clicking Zoom Full button you can see all simulation wave.

You have now completed simulation of your design using the ModelSim.

Now you can make FPGA pin assignments.

 

Test Bench                                                                                                                                     Vhdl_Code

 

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