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  * Project Introduction

  * VHDL Code

  * Test Bench

   * Simulation

Test Bench/ Debug and  Verify  The Code

Even though  there are no syntax errors in our program, we don’t know whether  it functions correctly or not. Therefore we should test the functionality of the code.

In this simple project of ours, we can simply verify the code even by eye. But in big projects including thousands of lines of codes, it’s not that simple. So we need to implement a comprehensive test for verification.

Usually simulation tools are used for this purpose since  it’s a lot easier to test the code in a simulation platform than directly testing on hardware.  Because in a simulation platform we can control and monitor  the whole environment including inputs, outputs and other signals.

To test our program we will write a test bench. With  this test bench we will simulate/test  our design using simulation tools (e.g. Modelsim).


Create A Test Bench

Test bench is a VHDL program which is used to simulate the produced code. Hence the same rules stated at the beginning apply to the test bench as well. So we’ ll begin the test bench program with stating  the library and packages.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

 Then we’ll define the entity.  But the entity of the test bench won’t contain any input or output ports.

ENTITY AND_GATE_TEST_BENCH IS
END AND_GATE_TEST_BENCH;

After defining entity, we’ll define the architecture of the test bench. Here we will include our model as a component to the test bench. Then we will define test signals to control the inputs and the outputs of the component. 


ARCHITECTURE behavior OF AND_GATE_TEST_BENCH IS

  -- Decleration of our model as a component
COMPONENT AND_GATE
PORT(
           in1     : IN  std_logic;
           in2      : IN  std_logic;
           out1   : OUT  std_logic
            );
END COMPONENT;
  --inputs
  signal in1 : std_logic := '0';
  signal in2 : std_logic := '0';
  --outputs
  signal out1: std_logic;


Now we will instantiate the component.

--Instantiate
U1: AND_GATE PORT MAP (in1   =>  in1,
                                                    in2   =>  in2 ,
                                                    out1=> out1   );
process
     begin                
          wait for 10 ms;   
          in1 <='1';
          wait for 10 ms;
          in2<='0';
          in1 <='1';
          wait for 10 ms;
          in1 <='1';
          wait for 10 ms;
          assert false
          report "simulation over"
         severity failure;
   end process;


And below is the complete code of the test bench.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY AND_GATE_TEST_BENCH IS
END AND_GATE_TEST_BENCH;

ARCHITECTURE behavior OF AND_GATE_TEST_BENCH IS

COMPONENT AND_GATE
PORT(
           in1     : IN  std_logic;
           in2      : IN  std_logic;
           out1   : OUT  std_logic            );
END COMPONENT;

  signal in1 : std_logic := '0';
  signal in2 : std_logic := '0';
  signal out1: std_logic;

BEGIN
    U1: AND_GATE PORT MAP (in1   =>  in1,
                                                        in2   =>  in2 ,
                                                       out1=> out1   );
   process
       begin                
             wait for 10 ms;   
             in1 <='1';
             wait for 10 ms;
             in2<='0';
             in1 <='1';
             wait for 10 ms;
             in1 <='1';
            wait for 10 ms;
            assert false
            report "simulation over"
            severity failure;
      end process;
   END;

 

project                                                                                                                                  Test_bench

 

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