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First of all, we will write the names of libraries and packages that we will need in our project.

In this project, well use IEEE.STD_LOGIC_1164 package of IEEE library

You can also define your own libraries. To learn how to do it, see Examples > Library.

library IEEE; -- Name of the library
use IEEE.STD_LOGIC_1164.ALL; -- name of the package in IEEE library

Abovefirst column includes library name. Second column includes package name. A library can contain more than one package. So we should state which package(s) well use in our project. After writinglibrary and package names, we must define an entitiy. This entity definesinput and output ports of the model that provide an interface to the outside world.

entity AND_GATE is
   Port ( in1       : in STD_LOGIC;
             in2        : in STD_LOGIC;
             out1 : outSTD_LOGIC );
  end AND_GATE;

Above we defined an output named out1 andtwo inputs named in1 and in2

Now, we must define the relation and function between the inputs and the output. To do this we must define an architecture.

architecture Behavioral of AND_GATE is
        out1<=in1 AND in2;               
    end Behavioral;

Congratulations ! Our first VHDL code has been completed.

Now it's the time for simulation and test.


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