In this project, we will design a 2-input AND GATE module.
What will we do in this project?
- WriteÂ the program code with VHDL
- Design a test bench to simulate the project
- Simulate the projectÂ by using Modelsim and Tina
Before writing the project code, letâ€™s take a quick look at VHDL.
VHDL (Very Highâ€“Speed Integrated Hardware Description Language) is one of the most popular hardware description languages. With VHDL, you can program the FPGA and simulate the program before downloading it to the FPGA.
In VHDL, there are two types of Â codes:
- Synthesizable Codes: are the codes which can be implemented as hardware on FPGAs. All VHDL codes are not synthesizable. ThereforeÂ FPGAÂ designersÂ shallÂ be carefull while choosing the codes (gurded block)
- Non-synthesizable Codes: are used for simulation purposes and can not be implemented on FPGAs. Â
VHDL has fourÂ design units:
- Entity: All inputs and outputs ofÂ the module are defined in this part.
- Architecture: Â Functions between inputs and outputs are defined in this part.
- Configurations: Architecture and Entity are associated.
- Packages : A collection of declarations that can be used in more than one design.