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 * Clock Generic

 * Decoder

 * Encoder

 * Edge Detector

 * Half Adder

 * Full Adder

 * Multiplexer

 * Paralel To Serial
   Converter

 * Serial To Parelel
   Converter

 * Shift Register

 * Parity  

  * Ram

Multiplexer

We will design a 4 to 1 Multiplexer in this project.

VHDL CODE 1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MUX_4_TO_1 is
           Port ( INPUT       :   in  STD_LOGIC_VECTOR (3 downto 0);
                      SEL            :   in  STD_LOGIC_VECTOR (1 downto 0);
                      OUTPUT   :   out  STD_LOGIC);
           end MUX_4_TO_1;

architecture Behavioral of MUX_4_TO_1 is
       begin
              with  SEL select
                        OUTPUT <= INPUT(0) when "00",
                                               INPUT(1) when "01",
                                               INPUT(2) when "10",
                                               INPUT(3) when "11",                    
                                                        '0'     when others;
       end Behavioral;

 

VHDL CODE 2

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_signed.all;

entity MUX_4_TO_1 is
               Port ( INPUT     : in  STD_LOGIC_VECTOR (3 downto 0);
                          SEL         : in  STD_LOGIC_VECTOR (1 downto 0);
                          OUTPUT : out  STD_LOGIC);
end MUX_4_TO_1;

architecture Behavioral of MUX_4_TO_1 is
      begin
           OUTPUT <= input(conv_integer(sel));
      end Behavioral;

Test Bench                                                                                                                                     Vhdl_Code

 

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