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 * Parallel To Serial
   Converter

 * Serial To Parallel
   Converter

 * Shift Register

 * Parity  

  * Ram

Parallel to Serial Converter

In this example we will design a Paralel to Serial Converter module. This module takes a 8 bit data as a input and send this data bit by bit as a output. We also add a start and a stop bits before and after the input data respectively in order to show the begining and end of the serial data.Both Start and Stop bits will be '1'.

This module has four inputs and one output.

In digital designs, a parallel to serial converter is the essential circuit to tranfer a data word out through a serial interface such as RS-232.

The wave diyagram of thedata transmission of the module is be as follows.

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ParalellToSerial is
        Port ( reset,clk,start : in STD_LOGIC;
                   data_in:in STD_LOGIC_VECTOR (7 downto 0);
                   data_out:out STD_LOGIC);
end ParalellToSerial;

architecture Behavioral of ParalellToSerial is
       signal DST:STD_LOGIC_VECTOR (7 downto 0):=(others=>'0');
       signal DATA,STOP:STD_LOGIC:='0';
begin
       process(reset,clk)
       begin
             if reset='1' then
                   DST<=(others=>'0');
                   DATA<='0';
                   STOP<='0';
            elsif rising_edge(clk) then
                  if start='1' then
                       DATA<='1';--start bit
                       STOP<='1';--stop bit
                       DST<=data_in;
                  else
                       DATA<=DST(7);
                       STOP<='0';
                       DST<=DST(6 downto 0)&STOP;
                  end if;
            end if;
      end process;
      data_out<=DATA;
end Behavioral;

After  we simulate the project with Modelsim , we’ll get the result given below:

 

 

Test Bench Vhdl_Code

 

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