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Shift Register

Shift register shifts data either left or right through a number of cascaded flip-flops.

In this example we will design a shift register with the shift right function through eight flip- flops.

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SHIFT_REGISTER is
     Generic( CAPACITY : integer := 8);
          Port  ( CLK            :  in  STD_LOGIC;
                      DATA          :  in  STD_LOGIC;
                      RESET      :  in  STD_LOGIC;
                     OUTPUT    :  out  STD_LOGIC);
     end SHIFT_REGISTER;

architecture Behavioral of SHIFT_REGISTER is
signal reg: Std_Logic_Vector(CAPACITY-1 downto 0):=(others=>'0');
begin
    process(CLK,RESET)
        begin
           if RESET = '1' then
                   reg<=(others=>'0');
            elsif rising_edge(CLK)   then
                     reg<= DATA & reg(CAPACITY-1 downto 1); --&= concatenation                   
            end if; 
  end process;
OUTPUT<=reg(0 );
end Behavioral;

After  we simulate the project with Modelsim , we’ll get the result below:

Test Bench                                                                                                                                     Vhdl_Code

 

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