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Clock Generic

We will design a clock module in this project. The modul has an generic value that both indicates upper value of clock period and allow the designer to change the clock frequency externally.

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CLOCK_GEN is
      generic (upper_level : integer := 3  );          
      Port ( CLK          : in  STD_LOGIC;
                 CLK_gen : out  STD_LOGIC);
end CLOCK_GEN;

architecture Behavioral of CLOCK_GEN is
      signal Counter,Counter_next: std_logic_vector(upper_level-1 downto 0):= (others =>'0');
begin
      process(CLK)
      begin
             if CLK= '1' and CLK'event    then                                                              
                   Counter<=Counter_next;
             end if;           
      end process;
      Counter_next<= Counter +1;
      CLK_gen<= Counter(Upper_level-1);
end Behavioral;

After  we simulate the project with Modelsim , we’ll get the result given below:

        Vhdl_Code

 

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