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Decoder

We will design a "2 to 4 decoder" module in this example.

                                

Truth table of the decoder

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DECODER is
       Port ( A1 : in  STD_LOGIC;
                 A2 : in  STD_LOGIC;
                 O1 : out  STD_LOGIC;
                 O2 : out  STD_LOGIC;
                 O3 : out  STD_LOGIC;
                 O4 : out  STD_LOGIC);
end DECODER;

architecture Behavioral of DECODER is
begin
          O1<= (NOT A1) AND (NOT A2);
          O2<= A1 AND (NOT A2);
          O3<=(NOT A1) AND A2;
          O4<=A1 AND A2;
end Behavioral;

After  we simulate the project with Modelsim , we’ll get the result given below:

                                                                                                                                    

 

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