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Edge Detector

1- Rising Edge Detect ( "0" to "1" transition)

We will design a edge detector module that detect the rising edge of any input signal and produce a pulse as a output

Block diagram of edge detector

 

 

                                                

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity edge_detector is
      Port ( clk               : in  STD_LOGIC;
                 signal_in   : in  STD_LOGIC;
                 output         : out  STD_LOGIC);
end edge_detector;

architecture Behavioral of edge_detector is
     signal signal_d:STD_LOGIC;
begin
    process(clk)
    begin
         if clk= '1' and clk'event then
               signal_d<=signal_in;
         end if;
    end process;
    output<= (not signal_d) and signal_in;
end Behavioral;

After  we simulate the project with Modelsim , we’ll get the result given below:

 

1- Falling Edge Detect ( "1" to "0" transition)

We will design a edge detector module that detect the falling edge of any input signal and produce a pulse as a output.

Block diagram of Edge detector

                                                                         

 

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity edge_detector is
      Port ( clk               : in  STD_LOGIC;
                 signal_in   : in  STD_LOGIC;
                 output         : out  STD_LOGIC);
end edge_detector;

architecture Behavioral of edge_detector is
    signal signal_d:STD_LOGIC;
begin
    process(clk)
    begin
        if clk= '1' and clk'event then
               signal_d<=signal_in;
        end if;
    end process;
    output<= (not signal_in) and signal_d ;
end Behavioral;

After  we simulate the project with Modelsim , we’ll get the result given below:

 

Test Bench Vhdl_Code

 

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