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 * Clock Generic

 * Decoder

 * Encoder

 * Edge Detector

 * Half Adder

 * Full Adder

 * Multiplexer

 * Paralel To Serial
   Converter

 * Serial To Parelel
   Converter

 * Shift Register

 * Parity  

  * Ram

Encoder

We will design 4 to 2 encoder module in this example.

 1) VHDL CODE(Sequential)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity encoder is
        Port (    reset    :  in  STD_LOGIC;
                     CLK      :  in  STD_LOGIC;
                     D_in     :  in  STD_LOGIC_VECTOR (3 downto 0);
                     D_out   :  out  STD_LOGIC_VECTOR (1 downto 0));
end encoder;

architecture Behavioral of encoder is
begin
     process(CLK,reset,D_in)
     begin
          if reset='1' then
                 D_out<= (others=>'0');
          elsif CLK= '1' and CLK'event then
                 case D_in is
                           when "0001"=> D_out<="00";
                           when "0010"=> D_out<="01";
                           when "0100"=> D_out<="10";
                           when "1000"=> D_out<="11";
                           when others=> NULL;
                end case;
          end if;
     end process;
end Behavioral;

After  we simulate the project with Modelsim , we’ll get the result given below:

 

 2) VHDL CODE (Concurrent )

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity encoder is
           Port (  D_in    : in  STD_LOGIC_VECTOR (3 downto 0);
                       D_out : out  STD_LOGIC_VECTOR (1 downto 0));
end encoder;

architecture Behavioral of encoder is
begin
      with  D_in select
                 D_out<= "00" when "0001",
                                  "01" when "0010",
                                  "10" when "0100",
                                  "11" when "1000",
                                  "ZZ" when others;   
  end Behavioral;                       

After  we simulate the project with Modelsim , we’ll get the result given below:

 

Test Bench Vhdl_Code

 

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