FPGA Center



 * Clock Generic

 * Decoder

 * Encoder

 * Edge Detector

 * Half Adder

 * Full Adder

 * Multiplexer

 * Paralel To Serial
   Converter

 * Serial To Parelel
   Converter

 * Shift Register

 * Parity  

  * Ram

Full Adder

We will design a Full Adder module in this eaxample. We will construct the Full adder module by using Half Adder Module.

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity full_adder is
      Port ( X          : in     STD_LOGIC;
                Y           : in     STD_LOGIC;
                Z           : in     STD_LOGIC;
               SUM      : out   STD_LOGIC;
               CARRY : out   STD_LOGIC);
end full_adder;

architecture Behavioral of full_adder is
COMPONENT half_adder
     PORT(
                   A : IN std_logic;
                   B : IN std_logic;
                   Sum : OUT std_logic;
                   Carry : OUT std_logic
                   );
END COMPONENT;

signal carry1,carry2,sum1:STD_LOGIC;
begin
Half_Adder_1: half_adder PORT MAP(
                                                                       A => X,
                                                                       B => Y,
                                                                       Sum => sum1 ,
                                                                        Carry => carry1
                                                                         );

Half_Adder_2: half_adder PORT MAP(
                                                                        A => sum1,
                                                                        B => Z,
                                                                       Sum =>SUM ,
                                                                       Carry =>carry2
                                                                     );
CARRY<=carry1 OR carry2;
end Behavioral;

After  we simulate the project with Modelsim , we’ll get the result below:

 

Test Bench                                                                                                                                     Vhdl_Code

 

Home | Fpga | VHDL | VHDL Dictionary | Digital Design | Simulation | PCB | Examples | Contact Us
Copyright © 2010 - 2013 FPGAcenter. All Rights Reserved.