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 * Clock Generic

 * Decoder

 * Encoder

 * Edge Detector

 * Half Adder

 * Full Adder

 * Multiplexer

 * Paralel To Serial
   Converter

 * Serial To Parelel
   Converter

 * Shift Register

 * Parity  

  * Ram

Half Adder

We will design a Half Adder  module in this example.

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity HALF_ADDER is
          Port ( A              :  in  STD_LOGIC;
                     B              :  in  STD_LOGIC;
                     SUM        : out  STD_LOGIC;
                     CARRY   : out  STD_LOGIC);
end HALF_ADDER;

architecture Behavioral of HALF_ADDER is
begin
     SUM       <= A XOR B;
     CARRY  <= A AND B;
end Behavioral;

After  we simulate the project with Modelsim , we’ll get the result given below:

Test Bench Vhdl_Code

 

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