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 * Parity  

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Project Description

In this project we'll design a module that find the even and odd parity of  any input signal.

       

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity PARITY is
        Port (  input                 :  in  STD_LOGIC_VECTOR (7 downto 0);
                    output_even   : out  STD_LOGIC;
                    output_odd     : out STD_LOGIC);
        end PARITY;

    
architecture Behavioral of PARITY is

    function Parity_odd(input:STD_LOGIC_VECTOR (7 downto 0)) return std_logic is
          variable temp: std_logic:='0';
          begin
               for I in 0 to 7 loop
                     temp:=temp xor input(I);
               end loop;
              return (not temp);
         end Parity_odd;

   function Parity_even(input:STD_LOGIC_VECTOR (7 downto 0)) return std_logic is
          variable temp: std_logic:='0';
            begin
                for I in input'range loop
                      temp:=temp xor input(I);
                end loop;
                return temp;
          end Parity_even;

begin
     output_even <=Parity_even(input);
     output_odd<=Parity_odd(input);
end Behavioral;

After  we simulate the project with Modelsim , we’ll get the result below:

 

 

Test Bench                                                                                                                                     Vhdl_Code

 

 

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