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Project Definition

In this project we will design a LCD module with VHDL

The LCd Module send data which gets as input to the LCD for displaying. Module will include the following controls.

In our project, we will apply 2 ms delay time between two commands or two data. Therefore we will define a variable called counter. We also will define a upper limit for Counter.

In our project we will use 50 Mhz system clock. And if we evaluate the upper limit according to the following equation we get 100000;

Upper limit = (delay time * system clock (Hz) = (0,02 s * 50000000 )= 100000

VHDL source code of the LCD has four state.

We define a variable called n in the VHDL source code. n indicates number of the commands which are sent to the LCD


You can find the asm chart of the project below.

You can find all documents of this project here.

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