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 * Project Definition

 * Add The ChipScope Pro
    Core To The Design

 * ILA Core Settings (1)

 * ILA Core Settings (2)

  * ChipScope Pro Analyzer

ChipScope Pro ILA Core Settings - Page 2

In Net Connections   we will make connection between the ports just created in ChipScope Pro Inserter and signals which determined in counter module. To do so click Modify Connection button.

Let's begin this part by making connection of the clock signal which determines the sampling rate. First select Clock Signals in the right pane. Type *clk* in pattern field and click on Filter button. After then select clk_BUFGP and click on Make Connections button. So that clk_BUFGP was connected to the clock signal.

Then follow the same process as stated above to make connection between Trigger Signal and start_IBUF.

Select Data Signals tab and connect the all counter signals to Data Signal Ports. Then click OK to close Select Net dialog box.  

You can easily realize that all units returned from red to black in ChipScope Pro Core Inserter dialog box. Save the design and click on Return to Project Navigator button to return the ISE design suit.

Now we can download the design to FPGA and  analyze  the design .

 

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