ChipScope Pro Analyzer
We will design a simple binary counter module in this example. Then we will download the design to FPGA and monitor the FPGA internal signals by using Chipscope Analyzer.
Counter module has start, stop and clk ports.
when start = '1' , the counter will be activated and start to count.
Introduction To The Project
We will use ILA (Integrated Logic Analyzer) Core in this example.
Note: ILA is one of the ChipScope Pro cores that captures signals based on trigger events
We will use start signal of the module as trigger signal. When start signal is '1' ILA starts to capture the samples from counter and stores them . Then we can monitor the stored signals by using ChipScope Analyzer in the PC.
We will use the following VHDL Code in our example.
entity simple_counter is
Port ( clkÂ Â Â : inÂ STD_LOGIC;
startÂ : inÂ STD_LOGIC;
output : outÂ STD_LOGIC_VECTOR (7 downto 0));
architecture Behavioral of simple_counter is
signal counter:STD_LOGIC_VECTOR (7 downto 0):=(others=>'0');
if start = '1' then
if rising_edge(clk) then
output <= counter;