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 * Project Definition

 * Add The ChipScope Pro
    Core To The Design

 * ILA Core Settings (1)

 * ILA Core Settings (2)

  * ChipScope Pro Analyzer

ChipScope Pro Analyzer

We will design a simple binary counter module in this example. Then we will download the design to FPGA and monitor the FPGA internal signals by using Chipscope Analyzer.

Counter module has start, stop and clk ports.

when start = '1' , the counter will be activated and start to count.


Introduction To The Project

We will use ILA (Integrated Logic Analyzer) Core in this example.

Note: ILA is one of the ChipScope Pro cores that captures signals based on trigger events

We will use start signal of the module as trigger signal. When start signal is '1' ILA starts to capture the samples from counter and stores them . Then we can monitor the stored signals by using ChipScope Analyzer in the PC.

We will use the following VHDL Code in our example.


VHDL KODU

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity simple_counter is
       Port ( clk        : in  STD_LOGIC;
                  start     : in  STD_LOGIC;
                  output  : out  STD_LOGIC_VECTOR (7 downto 0));
      end simple_counter;

architecture Behavioral of simple_counter is
      signal counter:STD_LOGIC_VECTOR (7 downto 0):=(others=>'0');
      begin
            process(clk,start)
                 begin
                      if start = '1' then
                           if rising_edge(clk) then
                                 counter<=counter +1;
                           end if;
                     else
                            counter<=(others=>'0');
                     end if;
            end process;
     output <= counter;
end Behavioral;

                                                                                                                                                                                  Vhdl_Code

 

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