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VHDL CODE

The VHDL code below represents a simple counter:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity COUNTER_1 is
      Port ( CLK          : in    STD_LOGIC;
                 OUTPUT : out STD_LOGIC_VECTOR (6 downto 0)  );
endCOUNTER_1;

architecture Behavioral of COUNTER_1 is
signal counter: std_logic_vector(6 downto 0):= "0000000";
   begin
        process(CLK)
            begin
                 if CLK= '1' and CLK'event then
                       counter<=counter + '1';
                 end if;
           end process;
      OUTPUT <= counter;
end Behavioral;

Just copy and paste this code into your FPGA design software then save to your computer.

 

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