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Project Definition

In this project, we will modify counter_1 module and create a new module called counter_2. We will add RESET, STOP/START and UP/DOWN control signals to counter_1 module.

The VHDL code of counter_2 will be written by using FSM metod. And we will also draw ASM chart of counter_2. After completing the project, we will simulate the project in TINA software.

Let's begin to write the VHDL code.

 

 

                                                                                                                                                                              Vhdl_Code

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