In this project, we will create a VHDL code that reads a text from text file saved in computer. Most of the VHDL commands used in this project are not synthesizable. Therefore we will use this project in Test Bench.
When Do We Need a Text File?
Suppose that you need to create a module that accepts a sequence of data and process these data with a special algorithm. So you created the module and you want to check if it works correctly. How can you do that?
Here is a solution: If you know what data are, create a new text file in your computer and write all possible data combinations in it. Then write a test bench of the module to test it, and make all connection between test bench and the text file.
That's the idea. Lets start...
First create a text file and write something in it. We wrote "FPGACENTER" and saved the file to computer as C:\fpga.txt .
Then write the VHDL code below.
entity read_file is
Port ( clk : inÂ STD_LOGIC );
architecture Behavioral of read_file is
type char_file is file of character;
file c_file_handle: char_file;Â Â
Â Â Â Â Â Â Â Â variable char_count: integer := 0;
type str_type is array( 9 downto 0) of character;
variable C: str_type;
if clk='1' and clk'eventÂ then
if char_count< 8 then
file_open(c_file_handle, "C:\fpga.txt", READ_MODE);
while not endfile(c_file_handle) loop
read (c_file_handle, C(char_count)) ;Â Â Â
char_count := char_count + 1;Â
After we simulate this project with Tina, we get the result below: