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A Sample Package Code

The Sample Package Code consists two function and a procedure as shown below.

Functions

Procedure

 

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package OR_XOR_AND is 

            type newtype  is
                    record
                          type_1        : std_logic_vector(3 downto 0);
                          type_2        : std_logic;
                   end record;

            -- constant declaration

             constant and_lenght               : integer := 3;

            -- fonction and procedure declaration

             function M_OR    (signal input1,input2: in std_logic_vector ) return std_logic_vector; 

             function M_AND (signal input1,input2: in std_logic_vector(3 downto 0) ) return       std_logic_vector;

             procedure M_XOR  (signal input1,input2: in std_logic_vector(3 downto 0);
                                                          signal output:  out std_logic_vector(3 downto 0));


  end OR_XOR_AND;

 

package body OR_XOR_AND is

-- function example 1
function M_OR    (signal input1,input2: in std_logic_vector ) return std_logic_vector is
variable temp     : std_logic_vector(input1'range);
     begin
          for I in input1'range loop
               temp(I) := input1(I) or input2(I);
          end loop;
         return temp;
    end M_OR;

-- function example 2
function M_AND (signal input1,input2: in std_logic_vector(3 downto 0) ) return std_logic_vector is
variable temp     : std_logic_vector(and_lenght downto 0);
       begin
            for I in 0 to input1'high loop
                   temp(I) := input1(I) and input2(I);
            end loop;
           return temp;
      end M_AND;

-- Procedure example
procedure M_XOR   (signal input1,input2: in std_logic_vector(3 downto 0); signal output: out std_logic_vector(3 downto 0)) is
variable temp     : newtype ;
      begin
           for I in 0 to  3 loop
                 temp.type_1(I) := input1(I) xor input2(I);
           end loop;
          output<= temp.type_1 ;
      end  M_XOR;

end OR_XOR_AND;

Copy above Code and paste your package file.

A Sample Test Code

In order to simulate the library in ModelSim you can write a test code like the following.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library My_library;
use My_library.OR_XOR_AND.all;

entity program_test is
       Port (    in1                 :  in    STD_LOGIC_VECTOR (3 downto 0);
                     in2                 :  in    STD_LOGIC_VECTOR (3 downto 0);
                     output_and  :  out  STD_LOGIC_VECTOR (3 downto 0);
                     output_or     :  out  STD_LOGIC_VECTOR (3 downto 0);
                     output_xor   :   out  STD_LOGIC_VECTOR (3 downto 0));
       end program_test;

architecture Behavioral of program_test is
      begin
          output_and <=M_AND(in1,in2);
          output_or<=M_OR(in1,in2);
           M_XOR(in1,in2,output_xor);
     end Behavioral;

Now you can simulate the test program in the Modelsim

 

 

Test Bench                                                                                                                                     Vhdl_Code

 

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