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Test Bench VHDL Code

LIBRARY ieee;
USE
ieee.std_logic_1164.ALL;
USE
ieee.std_logic_unsigned.ALL;
USE
ieee.numeric_std.ALL;
 

ENTITY Test_bench_period IS
END Test_bench_period;
 
ARCHITECTURE behavior OF Test_bench_period IS  
 
    COMPONENT PeriodMeasurement
          PORT(  clk      : IN  std_logic;
                        reset  : IN  std_logic;
                        start   : IN  std_logic;
                        input  : IN  std_logic;
                       done   : OUT  std_logic;
                       output : OUT  std_logic_vector(9 downto 0)         );
          END COMPONENT;

       --Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal start : std_logic := '0';
signal input : std_logic := '0';

      --Outputs
signal done : std_logic;
signal output : std_logic_vector(9 downto 0);

   -- Clock and input signal period definitions
constant clk_period : time := 20 ns;
constant SIGNAL_PERIOD: time:= 12000200 ns;

BEGIN

-- Instantiate the Unit Under Test
uut: PeriodMeasurement PORT MAP ( clk => clk,
                                                                     reset => reset,
                                                                     start => start,
                                                                     input => input,
                                                                     done => done,
                                                                     output => output );

   -- Clock and input signal process definitions

clk <= not clk after clk_period/2;
input<= not input after SIGNAL_PERIOD/2;   

   -- Stimulus process
  U1: process
             begin
                 reset<='1';
                 wait for 5 ms;
                 reset<='0';
                 wait for 5 ms;
                 start<='1';
                 wait for 200 ns;
                 start<='0';
                 wait for 40 ms;         
                 assert false
                 report  "Simulation over "
                 severity failure;
      end process;
END;

After  we simulate the Test Bench with ModelSim, we’ll get the result below:

 

project                                                                                                                                 

 

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