In this example we will design a¬† module that ¬†measure ¬†the period of any ¬†periodic signal.
We will started the project with preparing the ASM chart of period finder module. Then we will write the VHDL code. After that we will¬† create a test bench¬† and simulate the module using its TEST bench in model sim for verification.
Find the Period of a¬† signal
To find the period of a project ¬†,
First¬† we count the number of the sytem clock cycles between two rising edges of input signal. Then we multiply the number of clock cycles and period of System clock.
For example,¬† if the period of the system clock is Tclk and the number of clock cycles between two rising edges is N , the period of the signal is Tout= N x Tckl;
We will use 50 Mhz (20 ns) for this project.
We will define two variables called counter and N: Counter ¬†counts ¬†from 0 to 49 999 and when it reaches the maxumimul value, it returns 0 agen and increments the N by ¬†1 . And¬† N gives us peiod of the input signal in miliseconds.
Note: In this project we find the period of signal in miliseconds. ¬†So ¬†we take the maximum value ¬†of counter as 49 999(20 ns*50 000= 1ms);.
The program includes 3 states
Note: In order to detect rising edge of input signal a edge detector is used.
To see information about edge detector click here.
Now we can draw the ASM Chart that helps us to write VHDL code.