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FPGA ARCHITECTURE

FPGA is basically consists of Logic Cells, I/O Blocks (Input/Output) and interconnections.

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Logic-Cell         
                                                                                            

Logic Cells form the main structure of FPGAs. A Logic-Cell consists of one Lookup Table (LUT), one D-Flip Flop and one 2 to 1 Multiplexer.

                                   LUT
LUTs are actually small memories (RAM) that fulfill logic operations. An N-input LUT refers to a 2 eN memory.
As a result of combination of thousands of Logic Cells, complex and large programs are created.

Interconnections of logic cells are provided by programmable switches and matrix formed data paths (according to the installed program FPGA).

FPGA design defines the set of connections between logic functions, by determining functions of each of the logic cells and status (open /closed) of programmable switches.


FPGA Pins

FPGA pins are generally divided into two categories.

a) Dedicated pins

20% to 30% of all the pins of an FPGA are reserved. According to the special functions they realized, these pins are divided into three categories.

b) User Pins:

These are standard I/O pins that can be configurable by user. They are divided into three categories such as Input, Output, Input/Output.Each I/O pin is connected to a I/O cell in FPGA. Power needed by I/O cells is provided by VCCIO.

Despite having more than one VCCIO pins, all pins with the same voltage to feed in former FPGA 's.

Whereas in the new production FPGAs, I/Os can be divided into groups and these groups can be fed from different voltages. So, a group of I/O pins can be working with 3.3 V, while other groups of I/O pins work with 2.5 volt.


CLOCK and GLOBAL LINES


FPGA designs are usually synchronized. FPGA designs are based on clock signal and D Flip-Flops in FPGA change states with the help of clock signals.

In a synchronized designs, clock signal should trigger all flip-flops at the same. Otherwise there will be electrical and timing problems in FPGA.

In order to get rid of these problems,  FPGA manufacturers developed a special internal connection, "Global Routing" or "Global Line" so-called.

Through this connection, simultaneous access of clock signal to all Flip Flops within the FPGA is provided.
Therefore the clock must be feeded through FPGA’s reserved clock pins.


RAM Blocks


In almost all of today's FPGAs, memory units called RAMs are allocated. They are used for temporary storage needs which occur during the operation of logic circuits. This RAMs can support single or multiple access.

With multiple access, multiple applications can run read /write operations on the RAM. Multiple access is a good solution for transferring data between different process blocks that have different clocks.

For example, in order to transfer data to a data processing unit which works with 50 MHz clock from a data storage unit which works with 25 MHz clock, we can use a 2 port-RAM.

The data storage unit working with 25 MHz writes data to RAM, and data processing unit uses these data by reading it from RAM at 50 MHz.

For great RAM needs, there are Block RAMs in FPGA. However there are small scattered (distributed) RAMs which are interspersed among the logic cells for small data storage needs.

According to the needs, Xilinx uses some of the logic cells as RAM as a distributed RAM.
For the same purpose, Block RAMs in Altera FPGAs are shared in different sizes.

 

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