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FPGA CONFIGURATION

Contents on the FPGA are erased when the system's power is turned off or interrupted. So FPGA does not store the program on itself. Whenever you want to use FPGA, you need to upload a program to it.

Configuration Element

Because of the FPGA’s volatile nature, you must use configuration element with the FPGA. FPGA can be configurable by using one of these configuration elements below:

 

When is the FPGA Configured?

In fact, configuring (programming) the FPGA means that sending a significant data flow, that consists of 1 and 0’s to the FPGA by using the special pins.

FPGA 's must be programmed (configuration mode) so that it can be used (user mode).

Configuration Mode: When the power of the FPGA is turned on,  FPGA passes to configuration mode. FPGA is idle in this mode and all outputs are in inactive status.

User Mode: After uploading the FPGA, it passes to user mode and all pins become active. So the FPGA can do its task given by user.

Configuration methods are identical in FPGA’s of Altera and Xilinx. One of  two interfaces below are used to configure the FPGA.

 

JTAG (Joint Test Action Group) Interface

It is an IEEE standard developed in 1980. Today, JTAG is the most common method used on integrated circuits for debugging. During the design, you must select JTAG compatible devices to use JTAG. ICs that supports JTAG, like FPGAs, have at least four additional pins listed below in the next title.

All of the FPGA I/O pins of the JTAG interface can be controlled. In this manner, the FPGA can be programmed using specific JTAG commands (proprietary JTAG commands).


How does JTAG work?

JTAG is a serial bus with five signals:

One or more devices can be connected to a JTAG port. JTAG chain is created in such cases like using of multiple devices. All TMS and TCK pins are connected directly to the devices. TDI pin of a device is connected to TDO pin of another device to form a chain. A master controller ends this chain.
http://www.fpganedir.com/FPGA/RES%C4%B0M/jtah.jpg

All devices in the chain have an ID. In this way, the computer can distinguish the devices in the chain.
JTAG pins are usually dedicated. So they are used only for this purpose.

A JTAG cable is used to connect the computer to the board that will be tested. This cable might have one of the interfaces of ethernet, usb or parallel.


Synchronous Serial Interface

Bits can be send to the FPGA synchronously with this one-bit data/clock interface. The five of the most important interface pins are the following:

Data / data0 : This is the configuration data bit. It is used as the input of the FPGA.

Clk / clk : It is the configuration clock bit. The configuration data is slided after all risng egde of this clock.

Prog_b / nconfig : This is an active low pin. When it goes low, the FPGA is reseted and its configuration is erased. If it goes low while the FPGA is in user-mode, the FPGA stops operation immediately and all I/Os go back into tri-state mode.

Init_b / nStatus : This is an active low pin. It indicates whether the FPGA is ready to start the configuration process.

Done / confDone : It is an output of the FPGA. If this bit’s value goes high (1), it means that the FPGA configuration is completed and it goes to the user mode.

The init_b and done pins are open-collector pins, so we have to use pull-up resistors for these pins.

                                                                     File:Opencollector.jpg

Detailed information about configuration can be seen on Altera page of our site.

 

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