FPGA Center


As you remember, FPGAs are programmable hardwares.

Programming the FPGAs are necessary in order to make them ready for use. (ISE Compiler for Xilinx, and Quartus II for Altera are used for this purpose.)

Two methods are used to program the FPGA.

Logic gates and tools in the library of the compiler program ( ISE, Quartus, etc)  are used in graphical design method.
HDL is a programming language which helps to model a hardware. VHDL and Verilog are the most widely used types of HLDs. We use VHDL language in our examples.


There is no any important inability or any superiority between VHDL and Verilog. Both languages can be used to program the FPGAs. Since we are familiar with VHDL, our examples are written in this language.

Both graphical method and VHDL can be used while designing the program. Şematiklerini create your models created with HDL, as the graphical design can continue.

You can create schematics of you model by using HDL then continue to design with this graphical model.
Here is a simple example which is designed with both VHDL and graphical design. It’s a half

First, select an XOR and an AND gate in the graphical design software. Then replace these gates in the schematic page as you see in the picture below. Then make the pin connections. That’s it! You finished the design of your half adder by using graphical method. The other method is to write the VHDL code.


To describe the hardware of a half adder, write a VHDL code like below:

library IEEE;
entity HALF_ADDER is
       Port ( A              :  in  STD_LOGIC;
                  B              :  in  STD_LOGIC;
                  SUM        : out  STD_LOGIC;
                  CARRY   : out  STD_LOGIC);
       end HALF_ADDER;
architecture Behavioral of HALF_ADDER is
          SUM       <= A XOR B;
           CARRY  <= A AND B;
    end Behavioral;

After compiling each designs, we get the same program files created by these different methods.

More detailed information about VHDL can be found in VHDL section of our site.

You can create schematic of HALF_ADDER described above, then continue with graphical design method. For more detailed examples, see My First Quartus Project



The created project goes through the following stages during the compilation process.

Analysis and Synthesis: In this section, the compiler program decides whether the hardware is suitable, by analyzing the code or project. If translation to hardware of the software is possible, the code is synthesized and the RTL scheme is created.

RTL (Register Transfer Level) means the specification of the design of your code in terms of register
level. In other words, RTL is a simple expression of the VHDL code with the corresponding logic circuits.

Determining Constraints: The constraints must be declared on the program file before creating our project. Timing constraints (if applicable) and pin constraints (assigning FPGA pins to the created ports) are the two important constraints.

Place ve Routing: The compiler
program determines logic elements to be replaced and the connections between the pins and the logic elements, taking into account the constraints.

The Program File Generation: After Place and Routing, the compiler program creates appropriate programming files that will be downloaded to the devices.

If the program will be uploaded to the FPGA directly, JTAG file is created. If a configuration element or a flash memory will be used, the program
files which the devices support are used.

Uploading The Program: After all
the above processes completed, the program file is donloaded to  the FPGA or configuration elements. Thus, the FPGA is configured.

NOTE: For more detailed information about the FPGA configuration see the FPGA Configuration page.


























Test Bench                                                                                                                                     Vhdl_Code


Home | Fpga | VHDL | VHDL Dictionary | Digital Design | Simulation | PCB | Examples | Contact Us
Copyright © 2010 - 2013 FPGAcenter. All Rights Reserved.