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Replacing Circuit Elements With CAPTURE Application

Open Power page then click Place>Part.



Select FPGA library that you will use in the search box of the Place Part window.



Part A of the Schematic file contains Power pins of FPGA. Add this to the schematic file.



Select place wire on the side menu then join the GND pins.



Select place ground on the side menu then add this to the drawing.



Add VCC to the drawing in the same way. (Capsym)


Save the page then open the configuration page. And add Part C of the FPGA. Make the conenctions specified below. In this example, FPGA’s JTAG connections are defined and a connection extension is formed for CLK. So clock connection can be done in I_O page.


(R: in the analag library, Header: in the connector library)



Close the I_O page after saving data.  Add the Part B of the FPGA here. We will create VCC, GND and CLK connections by using four FPGA I/O pins in this example.



As you can see in the picture above, there are some question marks (e.i. U?B, J?,R?) on the joint signs.  To solve this problem click SCHEMATIC in the Project Manager window then click Tool>Annotate.

 

Select Update entire design then click OK.



No longer you will see the question marks in the drawings. Yo will see the numbers instead of question marks.
After this, you can define all the footprints of the other components.

Test Bench                                                                                                                                     Vhdl_Code

                                                                                                                                                                                                                                                                   

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