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DEBUGGING AND PROGRAM VERIFICATION

Why Simulation?

Although our program does not contain syntax errors, we may not sure it gives the results we want from our program exactly.

Especially in larger programs, before the FPGA is uploaded; it should be checked that the program is working properly and possible logical errors must be eliminated. Otherwise we may get unexpected results. Therefore, we should prepare a test program for our code in order to test it in any simulation platform.

Created VHDL code can be tested by creating TEST BENCH.

We simulate our designs on our site by using ModelSim and Tina softwares.

                                

 

 

 

 

                                                                                                                                  Test_bench

                                                                                                                                    

                                                                                                                                                                                                                                                                   

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