FPGA Center



 * Simulation Flow

 * Creating Library

 * Compiling File

 * Loading Design

 * Simulation

 * Defining Special Signal

  * Adding Breakpoint

Creating Library

Before starting simulation with MODELSIM, we need to create a library and compile the source code in the library.
Change the file location of your code on File> Change Directory.

This change helps you to add or save files easily to the library therefore you will not need to search files everytime. This process is not a necessary process. It only helps the designer.

1

Write the name of the library you will create in the Library Name section. Then ModelSim gives a default name as “work” for your library.

2

After clicking OK button, the following expressions are created in the Transcript section:

vlib work
vmap work work

3
                     

                                                                                                                                  Test_bench

                                                                                                                                    

                                                                                                                                                                                                                                                                   

Home | Fpga | VHDL | VHDL Dictionary | Digital Design | Simulation | PCB | Examples | Contact Us
Copyright © 2010 - 2013 FPGAcenter. All Rights Reserved.