FPGA Center

 * Simulation Flow

 * Creating Library

 * Compiling File

 * Loading Design

 * Simulation

 * Defining Special Signal

  * Adding Breakpoint

Loading The Design

In the ModelSim Transcript window, enter the command below:

vsim -voptargs="+acc" rs232rx (name of the project)

is the command for vsim, and this provides the projects readiness for debugging.


After loading the design, you can see the hierarchical structure of the design in the sim group of the Workspace window.


You can open or close each window seen above from the view menu.

NOTE: Loading process can be done by right clicking the name of the program to be loaded and then selecting the Simulate.





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